The invention relates to electronic circuit design and specifically to an interactive environment to support circuit design, characterization, analysis, model development, and plan development and usage.
Circuit level designers typically develop electronic circuits using plans, the most commonly encountered plans being Characterization Plans and Synthesis Plans which have much in common, though their end purpose is very different. In both cases, designers need tools to assist in characterizing and verifying the circuit (i.e. acquiring characterization results for the circuit through simulation), tools to assist visual and data processing analysis of the characterization results, tools to assist in creation of behavioral models for a circuit, and to provide mechanisms to enable reuse of characterization efforts in development of plans and for characterization of other designs.
Traditionally these tools have been supplied piecemeal, often by a variety of different manufacturers, which leads to inconsistencies and to much lost time and money as developers learn to master multiple complex systems.
A primary goal of the invention is to support the plan development process as much as possible (characterization, model generation and synthesis plans), but also to provide a system that makes it easy to create and analyze characterization results even if no plan is being developed.
Although the invention can be used to run simulations to capture results, it is not merely a simulator front-end. Other applications may provide this particular functionality. The major features of the invention can be summarized as follows:
An environment which allows for interactive exploration of design characteristics, i.e. the ability to build/run tests and collect/analyze data.
The ability to generate and verify behavioral models for circuits.
Support for the development of reusable plans in Perl.
Provides libraries for storage of plans.
An intuitive GUI interface that allows the user to focus on the task at hand, rather than focusing on how to operate the tool.
Uses terminology familiar to analog designers when possible.
Does not require the plan developer to learn languages for standard functions, and for advanced users, allow the designer to accomplish all tasks using standard function sets including: Verilog-AMS, Perl and Matlab.
Straightforward integration of schematic-capture systems into the development and testing flow.
Components of a plan and the plan itself may be reused (e.g. a test to measure open loop gain could be shared for multiple op-amps tests).
Support for distributed processing and parameter sweep unrolling for simulations.